1. Field of the Invention
The present invention relates to a method of manufacturing an epitaxial silicon wafer and an epitaxial silicon wafer manufactured by the method.
2. Description of Related Art
For instance, for manufacturing an epitaxial silicon wafer used for a power MOS transistor, a substrate resistivity of a silicon wafer needs to be extremely low. As a technique for sufficiently reducing the substrate resistivity of the silicon wafer, there has been known a technique of doping arsenic (As) or antimony (Sb) as an n-type dopant for resistivity adjustment to molten silicone, in a pulling step (i.e., at the time of growing a silicon crystal) of a monocrystalline ingot of a material for a silicon wafer (hereinafter, referred to as a single crystal). However, since such a dopant is extremely volatile, it is difficult to sufficiently increase a dopant concentration in the silicon crystal, so that it is difficult to manufacture a silicon wafer having a resistivity as low as desired.
Accordingly, a silicon wafer having an extremely low substrate resistivity, which is doped with a highly concentrated phosphorus (P) as an n-type dopant having a relatively lower volatility than arsenic (As) or antimony (Sb), has been used.
However, in such an epitaxial silicon wafer, the highly concentrated the dopant contained in the silicon wafer diffuses over an epitaxial film in a heat treatment process in the course of formation of a semiconductor device (a solid layer diffusion phenomenon).
Particularly, when the dopant is phosphorus, since phosphorus has a diffusion speed faster than those of other dopants, a phenomenon of expansion in a transition width (a width of a region at and near an interface between the silicon wafer and the epitaxial film which have different dopant concentrations and in which the dopant concentrations change) notably occurs in the heat treatment process in the course of formation of a semiconductor device.
Since the expansion in the transition width adversely affects essential device-properties such as a breakdown voltage in a semiconductor device, an epitaxial silicon wafer having a narrow transition width and a sharp resistivity distribution between the silicon wafer and the epitaxial film even after the heat treatment process in the course of formation of the semiconductor device has been demanded. To cope with this demand, a study for providing such an epitaxial silicon wafer has been made (see, for instance, Patent Literature 1: JP-A-2011-155130).
Patent Literature 1 discloses that, by setting an oxygen concentration of the silicon wafer at 0.8×1018 to 1.3×1018 atoms/cm3, a highly concentrated the dopant contained in the silicon wafer is inhibited from diffusing over the epitaxial film in the heat treatment process in the course of formation of the semiconductor device.
However, it is found that, when a plurality of semiconductor devices are manufactured from a single epitaxial silicon wafer made by the method described in Patent Literature 1, variance in withstand voltages (BVdss) of the semiconductor devices sometimes becomes large. In view of the above, an epitaxial silicon wafer having a small variance in the withstand voltages of the semiconductor devices has been demanded.